It depends on the project.
It depends on the project. For SOCs that I was involved with (DSPs, mobile phone SOC, wifi SOC), you are bringing together a lot of different IP from various sources. There's no way to use these HLS tools unless the third parties feel like writing a model for their IP in your choice of HLS tool language. This means you would have gaps in your HL design everywhere their stuff fits in. Verification in the high level language would be tough work until those gaps are filled. No doubt guys like Intel can use the fancy HLS tools on their SOC because they own every module in the design. Same goes for the RISCV stuff: They can run Chisel sims because they wrote every part of the design in Chisel. The rest of us idiots are doing straight Verilog RTL because SOC level is more about gluing a lot of different modules together with low level logic. Maybe there's a tool here or there that generates a little Verilog from some other language for you but that is very piecemeal. It really is like building Word with assembler. But your job is more about linking together static libraries that already work. It's grunt work and nothing special. Being able to discover a bug via verification is the skillful part. This is where the cosimulation that MyHDL supports is so handy. Reading up on it a bit more, it sounds very promising for the future. The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator.
Posted by gluggymug on Jul 28, 2015, 2:25 AM
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- (1) Because it doesn't actually solve the problem.
- Every time fossil comes up, I hear this same issue - "why is there no rebase?" And honestly, I've never been able to get this argument.
- My biggest problem with running local LLMs on my M4 Max/128GB RAM is the prefill latency.
- Biggest problem with httpx I see is authors sanity https://github.com/encode/httpx/discussions/3784 .
- There aren't many situations today that make one think: Why doesn't this business have a website?
- > IAM can stay MS That's leaving the most critical component still with a US company.
Raise real-world problems, find people facing the same issue, and discuss solutions.5,000 issues0 comments
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(1) Because it doesn't actually solve the problem.
Every time fossil comes up, I hear this same issue - "why is there no rebase?" And honestly, I've never been able to get this argument.
My biggest problem with running local LLMs on my M4 Max/128GB RAM is the prefill latency.
Biggest problem with httpx I see is authors sanity https://github.com/encode/httpx/discussions/3784 .
There aren't many situations today that make one think: Why doesn't this business have a website?
> IAM can stay MS That's leaving the most critical component still with a US company.
I am very petty about this one bug and have a very old axe to grind that this reminded me of!
Not just the edge router.
It depends on the project.
It depends on the project. For SOCs that I was involved with (DSPs, mobile phone SOC, wifi SOC), you are bringing together a lot of different IP from various sources. There's no way to use these HLS tools unless the third parties feel like writing a model for their IP in your choice of HLS tool language. This means you would have gaps in your HL design everywhere their stuff fits in. Verification in the high level language would be tough work until those gaps are filled. No doubt guys like Intel can use the fancy HLS tools on their SOC because they own every module in the design. Same goes for the RISCV stuff: They can run Chisel sims because they wrote every part of the design in Chisel. The rest of us idiots are doing straight Verilog RTL because SOC level is more about gluing a lot of different modules together with low level logic. Maybe there's a tool here or there that generates a little Verilog from some other language for you but that is very piecemeal. It really is like building Word with assembler. But your job is more about linking together static libraries that already work. It's grunt work and nothing special. Being able to discover a bug via verification is the skillful part. This is where the cosimulation that MyHDL supports is so handy. Reading up on it a bit more, it sounds very promising for the future. The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator.
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