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Upstream Raspberry Pi 4 B support

The Raspberry Pi 4 B has a new brand SoC BCM2711 (1.5GHz Quad A72, VideoCore 6) - LPDDR4 (1-8 GB) - VIA Labs VL805 USB 3.0 Host controller (XHCI) - USB bridge with 2x USB 3.0 and 2x USB 2.0 ports - DWC2 controller with 1 USB C USB Host / Peripheral port - Gigabit Ethernet with BCM54213PE PHY - 2x Micro HDMI 2.0 slots - PCIe 2.0 bus with 1 lane (USB hub) - 40 bit DMA controller - GICv2 interrupt controller - new eMMC controller (support for DDR50) - 58 GPIOs - 6 UART - 5 SPI - 6 I2C (without clock stretch bug) - 2 DSI - 2 CSI - 2 PWM units with 2 channels - Cypress CYW43455 (802.11 b/g/n/ac Wifi chip via SDIO, Bluetooth 5.0 via UART) Upstream status: Component | Status | Assigned | --- | --- | --- pinctrl | Applied for 5.4 | - sdhci | Applied for 5.4 | - sdhci SD power support | Applied for 5.x | Nicolas Saenz Julienne i2c | Applied for 5.4 | - initial clock support | Applied for 5.4 | Stefan Wahren initial devicetree | Applied for 5.5 | Stefan Wahren bluetooth | Applied for 5.5 | Stefan Wahren thermal | Applied for 5.6 | Stefan Wahren hwrng | Applied for 5.6 | Stephen Brennan spi | Applied for 6.0 | Martin Sperl bcm2835-power | Applied for 6.0 | Stefan Wahren GENET | Applied for 5.5 | Matthias Brugger, Stefan Wahren GENET clocks | tbd | Unknown GENET auto power down | Applied for 5.16 | Florian Fainelli DMA arm32 | WIP | Nicolas Saenz Julienne DMA arm64 | Applied for 5.5 | Nicolas Saenz Julienne PCIe | Applied for 5.6 | James Quinlan, Nicolas Saenz Julienne PCIe CLKREQ# mo

Posted by lategoodbye on Jul 2, 2019, 6:13 PM

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reliability (Network)

Upstream Raspberry Pi 4 B support

lategoodbyeJul 2, 2019, 6:13 PM

The Raspberry Pi 4 B has a new brand SoC BCM2711 (1.5GHz Quad A72, VideoCore 6) - LPDDR4 (1-8 GB) - VIA Labs VL805 USB 3.0 Host controller (XHCI) - USB bridge with 2x USB 3.0 and 2x USB 2.0 ports - DWC2 controller with 1 USB C USB Host / Peripheral port - Gigabit Ethernet with BCM54213PE PHY - 2x Micro HDMI 2.0 slots - PCIe 2.0 bus with 1 lane (USB hub) - 40 bit DMA controller - GICv2 interrupt controller - new eMMC controller (support for DDR50) - 58 GPIOs - 6 UART - 5 SPI - 6 I2C (without clock stretch bug) - 2 DSI - 2 CSI - 2 PWM units with 2 channels - Cypress CYW43455 (802.11 b/g/n/ac Wifi chip via SDIO, Bluetooth 5.0 via UART) Upstream status: Component | Status | Assigned | --- | --- | --- pinctrl | Applied for 5.4 | - sdhci | Applied for 5.4 | - sdhci SD power support | Applied for 5.x | Nicolas Saenz Julienne i2c | Applied for 5.4 | - initial clock support | Applied for 5.4 | Stefan Wahren initial devicetree | Applied for 5.5 | Stefan Wahren bluetooth | Applied for 5.5 | Stefan Wahren thermal | Applied for 5.6 | Stefan Wahren hwrng | Applied for 5.6 | Stephen Brennan spi | Applied for 6.0 | Martin Sperl bcm2835-power | Applied for 6.0 | Stefan Wahren GENET | Applied for 5.5 | Matthias Brugger, Stefan Wahren GENET clocks | tbd | Unknown GENET auto power down | Applied for 5.16 | Florian Fainelli DMA arm32 | WIP | Nicolas Saenz Julienne DMA arm64 | Applied for 5.5 | Nicolas Saenz Julienne PCIe | Applied for 5.6 | James Quinlan, Nicolas Saenz Julienne PCIe CLKREQ# mo

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