On a related note: I wish that more CPUs had an explicit cache.
On a related note: I wish that more CPUs had an explicit cache. So data has to be explicitly loaded into cache, etc. Modern CPUs are NUMA. Don't treat memory as RAM any more, because that's not true. Biggest problem with this is that not all CPUs have the same amount of cache. But you can get around this by treating the cache as the low area of RAM, with instructions to get the amount of cache available. Especially if cache is also paged. Other issue with this is context switches, but this is conceptually no different than paging RAM to disk when required.
Posted by TheLoneWolfling on Oct 6, 2014, 12:43 AM
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- Unless it is running on a government issued iPhone, it is not the Individual #1 you are alluding to.
- Great job, will try it.
- I also have a 2014 CR-V and I hate this too.
- I wish there was a setting to make audio and video opt in per site.
- There sure are.
- I feel like it's once a week that HN surfaces some incredibly overhyped, low-on-the-hierarchy-of-evidence ( https://en.wikipedi...
Raise real-world problems, find people facing the same issue, and discuss solutions.9,000 issues0 comments
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Unless it is running on a government issued iPhone, it is not the Individual #1 you are alluding to.
NewGreat job, will try it.
NewI also have a 2014 CR-V and I hate this too.
NewI wish there was a setting to make audio and video opt in per site.
There sure are.
I feel like it's once a week that HN surfaces some incredibly overhyped, low-on-the-hierarchy-of-evidence ( https://en.wikipedi...
That usually works well enough for risc code.
> The Bulletin calls her Miss Swindell.
On a related note: I wish that more CPUs had an explicit cache.
On a related note: I wish that more CPUs had an explicit cache. So data has to be explicitly loaded into cache, etc. Modern CPUs are NUMA. Don't treat memory as RAM any more, because that's not true. Biggest problem with this is that not all CPUs have the same amount of cache. But you can get around this by treating the cache as the low area of RAM, with instructions to get the amount of cache available. Especially if cache is also paged. Other issue with this is context switches, but this is conceptually no different than paging RAM to disk when required.
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