I've been skimming through MyHDL stuff.
I've been skimming through MyHDL stuff. It does support RTL like Chisel supposedly. http://docs.myhdl.org/en/latest/manual/rtl.html So it should simulate RTL and give you cycle accurate waves. No gate level sim for either tool means you're dead meat which ever way you go, so I am not sure why I am even bothering to look at this stuff. The respective merits of each approach is somewhat pointless when crucial steps in the HW process are completely ignored. And now you are saying you don't test on the generated Verilog from Chisel? That's no good. No one should just run tests in Chisel. You're delivering HW not Chisel code as far as I am concerned. That's a few huge steps more in the flow that need vigorous testing. Where is the quality control? So much more logic is added to chips during/after synthesis these days and you have no way to get any of your tests running on that net list.
Posted by gluggymug on Jul 26, 2015, 4:17 AM
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some bike vendor told me that the biggest problem with regular to ebike conversion was that regular bike frames were not strong enough to...
I think of this as the kiosk economy.
What a goofy comment.
There's lots of evidence for positive influences of Caffeine on the body (some negative as well), especially the brain.
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I've been skimming through MyHDL stuff.
I've been skimming through MyHDL stuff. It does support RTL like Chisel supposedly. http://docs.myhdl.org/en/latest/manual/rtl.html So it should simulate RTL and give you cycle accurate waves. No gate level sim for either tool means you're dead meat which ever way you go, so I am not sure why I am even bothering to look at this stuff. The respective merits of each approach is somewhat pointless when crucial steps in the HW process are completely ignored. And now you are saying you don't test on the generated Verilog from Chisel? That's no good. No one should just run tests in Chisel. You're delivering HW not Chisel code as far as I am concerned. That's a few huge steps more in the flow that need vigorous testing. Where is the quality control? So much more logic is added to chips during/after synthesis these days and you have no way to get any of your tests running on that net list.
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